Integrated circuits are often designed using complementary metal oxide semiconductor (CMOS) technology. With advances in CMOS technology, programmable circuits have been developed to realize a variety of functions, so long as the complexity of the desired function is not too high. An example of a reconfigurable circuit is a Field Programmable Gate Array (FPGA) circuit.
Programmable circuit designs will often use several transistors for each transistor of the target function, making the overall surface area required on a given die to be among the largest circuits made with a given technology. These relatively large integrated circuits often function near the capability limit of the current technology, such that manufacturers are constantly faced with reducing the size of their circuit designs in an effort to reduce problems in production.
One common function found on a programmable circuit is the configuration memory. CMOS-based programmable circuits, such as FPGA circuits, commonly include memory blocks having six transistor (6-T) bit cells, organized into rows and columns to form a matrix of 6-T bit cells. All the 6-T bit cells in a row of a CMOS memory block are typically accessed simultaneously. Likewise, all the 6-T bit cells in a column may be read or written using the same bit lines. Each 6-T bit cell typically requires 2 bit lines or sometimes 2 select lines. Unfortunately, this is problematic for memory within FPGA devices, because the metal layers are very crowded. As a result, FPGA memory often only dedicates 2 metal layers to the memory plane rather than the usual 3 or 4 in conventional ASIC designs, further increasing the size and complexity of corresponding bit cell designs.